The present invention relates generally to memory devices, and more particularly to distributed circuits to "turn off" word lines in a memory array.
Memory devices are integral to a computer system and to many electronic circuits. Continuous improvements in the operating speed and computing power of a central processing unit (CPU) enable operation of an ever-greater variety of applications, many of which require faster and larger memories. Larger memories can be obtained by shrinking the geometry of the memory cells and the data/control lines within the memory devices.
Smaller circuit geometry and increased integration in memory devices present various design issues. For example, reduction in the width (or pitch) of the control lines (e.g., word lines) results in higher line resistance. Narrow line pitch is especially problematic because the word lines are conventionally fabricated on a polysilicon layer that exhibits higher resistance than other materials such as metals. Thus, for a word line driver of a particular size, the higher line resistance increases the charge and discharge times of the line, which cause a corresponding increase in the access time of the memory cells within the memory device. In addition, with increased integration density, the number of memory cells coupled to each word line increases. As a result, the word line drive circuit may be required to have a larger current driving capability, which typically corresponds to larger die area and higher power dissipation, both of which are undesirable.
To address these design issues, some memory architectures employ a hierarchical word line structure having main word lines and split sub (or segmented) word lines. The segmented word lines are typically fabricated on a polysilicon layer and have relatively higher resistance. The main word lines are less resistive conductive lines, and are typically fabricated as on a metal layer. Further, each main word line is typically fabricated over and along an associated set of segmented word lines. The main word line is stitched, at various locations along the length of the main word line, to each associated segmented word line. This "metal strapping" reduces the resistance of the word line, which reduces the propagation delays through the word line and improves access time.
Examples of hierarchical word line structures in memory devices are described in U.S. Pat. No. 5,148,401, issued to Sekino et al., U.S. Pat. No. 5,812,483 issued to Jeon et al., U.S. Pat. No. 5,835,439 issued to Suh, and U.S. Pat. No. 5,875,149 issued to Oh et al. These patents are incorporated herein by reference.
As can be seen, memory architectures that decrease the charge or discharge time of word lines with minimal increase in circuit size and power consumption are highly desirable.